In recent years, various wired or wireless communication systems have been researched and developed. Accordingly, D/A converters for higher speed communications having conversion rates of several hundreds MHz to several tens GHz have become essential. Since D/A converters for communications are particularly desired to have low distortion characteristics, various circuit techniques have been suggested. Current steering D/A converters capable of performing high speed operations are typically used as D/A converters for communications.
FIG. 1 illustrates the overall structure of a conventional current steering D/A converter. In the D/A converter 100, outputs of a plurality of current sources 104-1 through 104-m are respectively coupled to inputs of differential switch circuits 105-1 through 105-m to form a current switch circuit. Output terminals of two of the differential switch circuits 105-1 through 105-m are commonly coupled to a non-inverting output terminal DAOUT and an inverting output terminal NDAOUT of the D/A converter 100. The output terminals DAOUT and NDAOUT are coupled to load resistors 106-1 and 106-2, respectively.
A current of each current source 104-1 through 104-m is set to a value weighted by a bias voltage Vbias generated by a bias circuit 101, and combinations of the values represent n bits, i.e., 2n steps.
Furthermore, n-bit digital data D0-Dn−1, which are input to the D/A converter 100, are converted into digital signals S1-Sm by a decoder circuit 102. Switch driver circuits 103-1 through 103-m synchronize the digital signals S1-Sm with a system clock CLK and input the signals to the differential switch circuits 105-1 through 105-m.
In this circuit structure, the differential switch circuits 105-1 through 105-m allow currents from the current sources 104-1 through 104-m to flow to the non-inverting output terminal DAOUT or to the inverting output terminal NDAOUT, depending on the digital signals S1-Sm. The currents are summed at the terminal and then converted into differential analog output voltages at the load resistors 106-1 and 106-2.
Note that a differential output structure is typically used for a D/A converter for communications to reduce even harmonic distortion and common mode noise.
FIG. 8 illustrates a circuit structure of a conventional current switch. FIG. 8 is a circuit diagram of a current switch including a current source 104-1 and a differential switch 105-1. The current source 104-1 includes two P-channel transistors TP201 and TP202. Bias voltages Vbias11 and Vbias12 are applied to gates of the transistors TP201 and TP202, respectively. The differential switch circuit 105-1 includes two P-channel transistors TP211 and TP212 of which source terminals are coupled to each other. Complementary digital signals DS and NDS are input to gate terminals of the transistors.
However, where the current switch of FIG. 8 is used for the D/A converter of FIG. 1, the signals DS and NDS are inverted or not inverted, depending on an input digital code. This causes noise dependent on the input digital code, and affects an analog output voltage to degrade distortion characteristics.
To solve the problems mentioned above, a current switch shown in FIG. 9 was suggested. FIG. 9 illustrates a differential switch, in which a constant digital noise is generated in each digital code so that the digital code does not depend on an input digital code. In the current switch of FIG. 9, source terminals of P-channel transistors TP221, TP222, TP231 and TP232 are commonly coupled to an output of a current source 104-1. Drain terminals of the transistors TP221 and TP231 are commonly coupled to a non-inverting output terminal DAOUT, and drain terminals of the transistors TP222 and TP232 are commonly coupled to an inverting output terminal NDAOUT. Gate terminals of the transistors TP221, TP222, TP231 and TP232 are controlled by digital signals DS1, DS2, DS3, and DS4, respectively.
FIG. 3 is a logic table illustrating operation of the current switch shown in FIG. 9. In actual operation, the switch alternates between one of states 1 and 2, and one of states 3 and 4 in each clock cycle. That is, only one of the four switch transistors TP221, TP222, TP231 and TP232 is ON at any time. In all cycles, two of the transistors are alternately change the states, one from ON to OFF and the other from OFF to ON so that a constant digital noise is obtained in each cycle. As such, a constant digital noise can be generated at each digital code which does not depend on an input digital code. The effect of noise on an analog output voltage does not degrade distortion characteristics, since the noise is synchronized with a clock frequency (see, for example, Non-Patent Document 1).    [Patent Document 1] U.S. Pat. No. 7,034,733    [Patent Document 2] U.S. Pat. No. 6,842,132    [Non-Patent Document 1]    S. Park et al., “A Digital-to-Analog Converter Based on Differential-Quad Switching,” IEEE Journal of Solid-State Circuits, vol. 37, No. 10, October 2002.    [Non-Patent Document 2]    Douglas Mercer, “A Study of Error Sources in Current Steering Digital-to-Analog Converters,” IEEE 2004 Custom Integrated Circuits Conference.